avago technologies - 1 - description ACCL-9410 is a quad-channel bi-directional digital isolator. using capacitive coupling through an insulation barrier, the isolator enables high speed digita l transmissions. the device is capable of running at 25 mbd da ta rate, with propagation delay of 40ns. ACCL-9410 is available in 150mils narrow body 16-pin soic package. the isolator operates at 3.3v/5v supply. the electrical dc and timing ac specificat ions are specified over the temperature range of -40c to +125c. functional diagram features ? supply voltage: 3.3 v / 5 v ? wide operating temperature: -40 c to 125 c ? high data rate: 25 mbd ? low power consumption: 2 ma per channel ? low propagation delay: 40 ns max ? pulse width distortion: 8 ns max ? propagation delay part skew: 15 ns max ? propagation delay channel skew: 8 ns max ? output enable function ? safety and regulatory approvals (pending) ul 1577 applications ? industrial control isolated data interfaces, eg spi ? high speed digital systems ? isolated dc-dc converters ? logic level shifting 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 v dd1 gnd 1 v ia v ib v ic v od v e1 gnd 1 gnd 2 v e2 v id v oc v ob v oa gnd 2 v dd2 caution it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. the compone nts featured in this data sh eet are not to be used in military or aerospace applications or environments ACCL-9410 high speed quad-channel 3/1 digital isolator data sheet
avago technologies - 2 - ACCL-9410 data sheet ordering information ordering information to order, choose a part number from the part number column and combine with the desired opti on from the option column to form an order entry. solder reflow profile recommended reflow condition as per jedec standard, j-std- 020 (latest revision). non-halide flux should be used. regulatory information pending approval by the following organizations: ul pending ul1577, component recognition program truth table h - high level. l - low level, x - insignificant part number channel configuration option rohs compliant package surface mount tape & reel quantity ACCL-9410 quad, bi-directional, 3/1 -000e narrow body soic-16 x 50 per tube -500e x x 1000 per reel input supply vdd input output supply vdd output enable output remark h h h h or open h input logic high during normal operation. h l h h or open l input logic low during normal operation. h x h l z output is at high impedance state when output enable is set low l x h h or open h when input v dd is not powered, the output default is logic high. x x l x indeterminate when output v dd is not powered, the output goes into indeterminate state.
avago technologies - 3 - ACCL-9410 data sheet package outline drawings package outline drawings ACCL-9410 narrow body soic-16 package 0.228 (5.791) 0.244 (6.197) 0.386 (9.802) 0.394 (9.999) 0.152 (3.861) 0.157 (3.988) 0.013 (0.330) 0.020 (0.508) 0.040 (1.016) 0.060 (1.524) 0.050 (1.270) 0.060 (1.524) 0.054 (1.372) 0.068 (1.727) 0.004 (0.102) 0.010 (0.249) 0.016 (0.406) 0.050 (1.270) 0.010 (0.245) 0.020 (0.508) 0.008 (0.191) 0.010 (0.249) x 45 0 - 8 typ. dimensions: inches (millimeters) min max 0.286 (7.27) 0.085 (2.16) 0.025 (0.64 ) land pattern recommendation yyww nnnn device part number a ? eee lot id lead free avago date code 1 8
avago technologies - 4 - ACCL-9410 data sheet insulation and safety related specifications insulation and safety related specifications absolute maximum ratings recommended operating conditions parameter symbol ACCL-9410 units conditions minimum external air gap (clearance) l(101) 4.0 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 4.0 mm measured from input terminals to output terminals, shortest distance path along body. tracking resistance (comparative tracking index) cti 400 volts din iec 112/vde 0303 part 1 isolation group ii material group (din vde 0110, 1/89, table 1) parameter symbol min max units storage temperature t s -55 125 c operating temperature t a -40 125 c supply voltage v dd1 , v dd2 06v input voltage v i -0.5 v dd + 0.5 v output voltage v o -0.5 v dd + 0.5 v average output current i o 15 ma parameter symbol min max units operating temperature t a -40 125 c supply voltage (3.3v) v dd1 , v dd2 3.15 3.6 v supply voltage (5v) v dd1 , v dd2 4.5 5.5 v logic high input voltage v ih 2v dd v logic low input voltage v il 00.8v
avago technologies - 5 - ACCL-9410 data sheet electrical specifications (dc) electrical specifications (dc) over recommended temperature (t a = -40c to 125c) and supply voltage (4.5vv dd1 5.5v, 4.5vv dd2 5.5v), (3.15vv dd1 3.6v, 3.15vv dd2 3.6v), (4.5vv dd1 5.5v, 3.15vv dd2 3.6v) and (3.15vv dd1 3.6v, 4.5vv dd2 5.5v). all typical sp ecifications are at t a = 25 c. parameter symbol min. typ. max. units test conditions input supply current, no data [1] i dd1(0) 2.8 5 ma v dd1 = 3.6 v, dc 2.9 5 ma v dd1 = 5.5 v, dc input supply curr ent, 10mbd data (all channels) [2] i dd1(10) 3.7 6 ma v dd1 = 3.6 v, 5 mhz logic signal 4.1 7 ma v dd1 = 5.5 v, 5 mhz logic signal input supply curr ent, 25mbd data (all channels) [2] i dd1(25) 5.0 8 ma v dd1 = 3.6 v, 12.5 mhz logic signal 5.9 9 ma v dd1 = 5.5 v, 12.5 mhz logic signal output supply current, no data [3] i dd2(0) 6.5 10 ma v dd2 = 3.6 v, dc 6.6 10 ma v dd2 = 5.5 v, dc output supply current, 10mbd data (all channels) [4] i dd2(10) 7.6 11 ma v dd2 = 3.6 v, 5 mhz logic signal 8.1 12 ma v dd2 = 5.5 v, 5 mhz logic signal output supply current, 25mbd data (all channels) [4] i dd2(25) 9.2 13 ma v dd2 = 3.6 v, 12.5 mhz logic signal 10.3 15 ma v dd2 = 5.5 v, 12.5 mhz logic signal input current i i -10 10 a logic high output voltage v oh v dd -0.1 v dd vi o = -20 a, v i = v ih v dd -1.0 v dd vi o = -4 ma, v i = v ih logic low output voltage v ol 0.02 0.1 v i o = 20 a, v i = v il 0.14 0.4 v i o = 4 ma, v i = v il high level enable voltage v eh 0.7xv dd v low level enable voltage v el 0.3xv dd v
avago technologies - 6 - ACCL-9410 data sheet switching specifications (ac) switching specifications (ac) over recommended temperature (t a = -40c to 125c) and supply voltage (4.5vv dd1 5.5v, 4.5vv dd2 5.5v), (3.15vv dd1 3.6v, 3.15vv dd2 3.6v), (4.5vv dd1 5.5v, 3.15vv dd2 3.6v) and (3.15vv dd1 3.6v, 4.5vv dd2 5.5v). all typical sp ecifications are at t a = 25 c. parameter symbol min. typ. max. units test conditions propagation delay time to logic low output t phl 29 40 ns v dd1 = v dd2 = 3.3 v, c l = 15pf, cmos signal levels 27 40 v dd1 = v dd2 = 5 v, c l = 15pf, cmos signal levels propagation delay time to logic high output t plh 29 40 ns v dd1 = v dd2 = 3.3 v, c l = 15pf, cmos signal levels 27 40 v dd1 = v dd2 = 5 v, c l = 15pf, cmos signal levels pulse width t pw 40 ns cl= 15pf, cmos signal levels maximum data rate 25 mbd cl= 15pf, cmos signal levels pulse width distortion | t phl - t plh | pwd 0.3 8 ns v dd1 = v dd2 = 3.3 v, c l = 15pf, cmos signal levels 0.5 8 ns v dd1 = v dd2 = 5 v, c l = 15pf, cmos signal levels propagation delay channel skew t csk 2 8 ns cl= 15pf, cmos signal levels propagation delay part skew t psk 15 ns cl= 15pf, cmos signal levels propagation delay time of enable from v eh to v el t elh 8nsv dd1 = v dd2 = 3.3 v, c l = 15pf, cmos signal levels 6v dd1 = v dd2 = 5 v, c l = 15pf, cmos signal levels propagation delay time of enable from v el to v eh t ehl 26 ns v dd1 = v dd2 = 3.3 v, c l = 15pf, cmos signal levels 23 v dd1 = v dd2 = 5 v, c l = 15pf, cmos signal levels output rise time (10% - 90%) t r 3.5 ns v dd1 = v dd2 = 3.3 v, c l = 15pf, cmos signal levels 2v dd1 = v dd2 = 5 v, c l = 15pf, cmos signal levels output fall time (90% - 10%) t f 2.5 ns v dd1 = v dd2 = 3.3 v, c l = 15pf, cmos signal levels 2v dd1 = v dd2 = 5 v, c l = 15pf, cmos signal levels common mode transient immunity at logic high output | cm h |10kv/ ? sv cm = 1000 v, t a = 25 c, v dd = 5v, v o > 2v common mode transient immunity at logic low output | cm l |10kv/ ? sv cm = 1000 v, t a = 25 c, v dd = 0 v, v o < 0.8 v
avago technologies - 7 - ACCL-9410 data sheet package characteristics package characteristics all typical at t a = 25 c notes: 1. i dd1(0) is the supply current consumption at v dd1 when there is no signal to all inputs. 2. i dd1(f) is the supply current consumption at v dd1 when inputs are switching at the spec ified data rate, and outputs are switching at same data rate with no load. 3. i dd2(0) is the supply current consumption at v dd2 when there is no signal to all inputs. 4. i dd2(f) is the supply current consumption at v dd2 when inputs are switching at the spec ified data rate, and outputs are switching at same data rate with no load. 5. in accordance with ul 1577, each isolator is pr oof tested by applying an insulation test voltage 1800 vrms for 1 second (leakage detection current limit, i i-o 5 ? a). parameter symbol min. typ. max. units test conditions input-output insulation [5] v iso 1500 vrms rh < 50% for 1 min. t a = 25 c input-output resistance r i-o 10 15 v i-o = 500 v input-output capacitance c i-o 1.6 pf f=1 mhz, t a = 25 c package power dissipation p pd 155 mw performance figure 1 typical i dd1(0) vs temperature figure 2 typical i dd1(25) vs temperature 2.0 2.5 3.0 3.5 -50 -25 0 25 50 75 100 125 idd1, ma temperature, c vdd=3.3v vdd=5.0v 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -50 -25 0 25 50 75 100 125 idd1, ma temperature, c vdd=3.3v vdd=5.0v
avago technologies - 8 - ACCL-9410 data sheet performance figure 3 typical i dd2(0) vs temperature figure 4 typical i dd2(25) vs temperature 6.0 6.5 7.0 7.5 -50 -25 0 25 50 75 100 125 idd2, ma temperature, c vdd=3.3v vdd=5.0v 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -50 -25 0 25 50 75 100 125 idd2, ma temperature, c vdd=3.3v vdd=5.0v figure 5 typical propagation delay t plh vs temperature figure 6 typical propagation delay t phl vs temperature 20 25 30 35 40 -50 -25 0 25 50 75 100 125 tplh, ns temperature, c vdd=3.3v vdd=5.0v 20 25 30 35 40 -50 -25 0 25 50 75 100 125 tphl, ns temperature, c vdd=3.3v vdd=5.0v figure 7 typical pulse width distortion pwd vs temperature figure 8 typical propagation delay channel skew t csk vs temperature -1 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 pwd, ns temperature, c vdd=3.3v vdd=5.0v 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 tcsk, ns temperature, c vdd=3.3v vdd=5.0v
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago technologies and the a logo are tradem arks of avago technologies in the united states and other countries. all other brand and product names may be trademarks of their respective companies. data subject to change. copyright ? 2015-201 6 avago technologies. all rights reserved. pub-005306 C january 27, 2016 bypassing and pc board layout the ACCL-9410 digital isolator is easy to use. no external inte rface circuitry is required because its high speed cmos ic techn ology allows cmos logic to be connected directly to the inputs and outputs. as shown in figure 9, the external components required fo r proper operation are two bypass capacitors for decoupling the po wer supply. capacitor values should be 0.1 f and the capacitor be placed as close as possible to the isolator. the total lead le ngth between both capa citor ends and the power supply pins is not more than 20 mm. figure 9 typical schematic of ACCL-9410 on pc board 1 2 3 4 5 6 8 7 16 15 14 13 12 11 9 10 vdd 1 vdd 2 gnd 1 gnd 2 gnd 1 gnd 2 v ia v ib v ic v od v e1 v oa v ob v oc v id v e2 0.1 f 0.1 f
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